Extension and VLSI Implementation of the Majority-Gate Alg..
نویسندگان
چکیده
This paper presents the design and VLSI implementation of a new ASIC which performs in real-time the morphological operations of dilation and erosion. The ASIC's architecture is based on the extension of the majority-gate algorithm for morphological operations. The ASIC was implemented using a DLM, 0.7 ìm, CMOS, N-well process and it occupies a silicon area of 14.78mm2. Its maximum speed of operation is 92.5 MHz. Targeted applications include machine vision applications, where the need for short processing times is crucial. Subject terms : image processing, mathematical morphology, majoritygate, ASICs.
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